In digital communications, it is necessary to synchronize or time align a local receiver's clock to a transmitter's clock when the transmitter transmits a data signal to the receiver. A phase locked loop in the receiver performs this synchronization function by locking a voltage controlled oscillator to the transmitter's clock. The voltage controlled oscillator provides a clock signal for sampling the received data signal.
For example, a Digital Data Service (DDS) transmitter at a central office is used to transmit a digital data signal to a remote location over a twisted pair of wires. The DDS transmitter at the central office typically utilizes a transmit clock that is derived from a relatively accurate network source. However, the clock in the receiver is typically generated by a voltage controlled oscillator that has a frequency that may vary slightly from the frequency of the network source. These variations in the receiver's clock frequency may occur for a number of reasons. For instance, manufacturing tolerances for voltage controlled oscillators typically result in individual oscillators that produce frequencies having some variance about a mean value. To correct for these frequency errors in the receiver, the DDS receiver must adapt its sampling frequency to match that of the DDS transmitter. Thus, the DDS receiver utilizes a timing loop having timing loop parameters to synchronize the receiver's clock with the transmitter's clock.
The values of the timing loop parameters determine the increments that the receiver will use to alter or adjust its clock frequency to match the frequency of the transmitter's clock. Typically, large timing loop parameter values cause the timing loop to alter the receiver's clock frequency to approach the transmit clock frequency more quickly. However, these larger values of the timing loop parameters also introduce additional jitter into the receiver when the frequency error between the transmit clock and the receiver's clock is relatively small. The increased jitter is a result of the relatively rapid changes in the receiver's clock frequency about a mean value that result from the relatively large timing loop parameter values. Smaller timing loop parameter values do not introduce as much jitter. Unfortunately, smaller timing loop parameter values also increase the time required for the timing loop to initially acquire synchronization when a large frequency error exists between the transmitter's clock and the receiver's sample clock. It is typical to maintain the larger timing loop parameters for a predetermined time that is long enough to acquire the timing when the initial frequency error is the maximum frequency error expected. The larger timing loop parameters could be maintained for a shorter amount of time when the initial frequency error is less than the maximum frequency error expected. However, when the data transmission from the DDS transmitter to the DDS receiver first begins, the difference between the frequency of the transmitter's clock and the receiver's clock is unknown. Thus, it is difficult to optimize the timing loop's performance for the majority of the cases where the initial frequency error is less than the maximum frequency error expected.
Since the time to acquire timing by a receiver is an accepted measure of performance, it is desirable to acquire timing as fast as possible. Therefore, what is needed is an apparatus or method that rapidly synchronizes or trains a receiver's clock to a transmitter's clock over a broad range of frequency errors.